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RISC Architecture - The Computer with Speed in Mind



The M series chip in MacBooks have brought about a revolution. Now we have processors providing higher speed, with lower battery usage. No wonder we hear ARM based laptops running 18 to 24 hours, on a single charge. This has even disrupted legacy chips like x86/x64 from market monopoly.


Behind the Scenes

All this is made possible by a chip architecture known as RISC. The acronym for Reduced Instruction Set Computer.  As the name suggests, here less is more. Lower instruction set leads to less complexity and higher performance. Data is stored in registers and executed result in memory.


The Cycle

Every instruction execution goes through the following stages

  1. Instruction fetch: In this stage, the processor fetch code for execution, from registers
  2. Instruction decode: The code is then decoded, and analyzed
  3. Operand fetch: The operands required is retrieved from registers
  4. Instruction execution: The code is executed by the processor.
  5. Result storage: The final data is stored in register or memory
Here the RISC schema uses a concept called pipelining to improve efficiency. Each instruction takes one clock cycle to complete. Through parallel computation, multiple instructions are started and run on various stages of execution. For example, when one instruction is decoded, another begins the fetch stage, while the third would have completed execution. 
There is no limit to how many instructions can be run at any given time. It primarily depends on the hardware and memory capability.

Other Points
  • Frequently used operand is stored in CPU register.
  • More number of registers can be utilized to reduce memory traffic
  • Reduced register to memory operations

Uses
  1. Used in mobile phones, tablets and laptops
  2. Used in smart devices (Internet of things) where power consumption needs to be low.



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